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Industrial Temperature K4E661612D,K4E641612D CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Normal or Low power) are optional features of this family. All of this family have C A S -before-R A S refresh, R A S -only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated u s i n g S a m s u n g s a d v a n c e d C M O S p r o c e s s t o r e a l i z e h i g h b a n d - w i d t h , l o w p o w e r c o n s u m p t i o n a n d h i g h r e l i a b i l i t y .
FEATURES
* Part Identification
- K4E661612D-TI/P(3.3V, 8K Ref.) - K4E641612D-TI/P(3.3V, 4K Ref.) * R A S-only and Hidden refresh capability * Fast parallel test mode capability * Self-refresh capability (L-ver only) * Active Power Dissipation Unit : m W Speed -45 -50 -60 8K 324 288 252 4K 468 432 396 * LVTTL(3.3V) compatible inputs and outputs * Early Write or output enable controlled write * JEDEC Standard pinout * Available in Plastic TSOP(II) packages * + 3 . 3 V 0 . 3 V p o w e r s u p p l y * I n d u s t r i a l T e m p e r a t u r e o p e r a t i n g ( - 4 0 ~ 8 5 C ) * Extended Data Out Mode operation * 2 CAS Byte/Word Read/Write operation * C A S-before-R A S refresh capability
*
Refresh Cycles
Part NO. K4E661612D* K4E641612D Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS UCAS LCAS W Control Clocks Vcc Vss
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
*
Access mode & R A S only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) C A S - b e f o r e -R A S & H i d d e n r e f r e s h m o d e : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Refresh Control Memory Array 4,194,304 x 16 Cells Refresh Timer Row Decoder S en s e A m p s & I/ O
Lower Data in Buffer Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer
DQ0 to DQ7
* Performance Range Speed -45 -50 -60
Refresh Counter
OE D Q8 to DQ15
tR A C
45ns 50ns 60ns
tC A C
12ns 13ns 15ns
tR C
74ns 84ns 104ns
tH P C
17ns 20ns 25ns
A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
S A M S U N G E L E C T R O N I C S C O . , L T D . reserves the right to change products and specifications without notice.
Industrial Temperature K4E661612D,K4E641612D CMOS DRAM
PIN CONFIGURATION (Top Views)
* K4E661612D-T * K4E641612D-T
V CC
DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product
Pin Name A0 - A12 A0 - A11 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C
Pin function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
Industrial Temperature K4E661612D,K4E641612D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VC C supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS Address Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Units V V C W mA
CMOS DRAM
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VC C VSS VIH VIL Min 3.0 0 2.0 -0.3 *2
(Voltage referenced to Vss, T A= -40 to 85C)
Typ 3.3 0 Max 3.6 0 Vcc+0.3 0.8
*1
Units V V V V
*1 : Vcc+1.3V at pulse width 15ns which is measured at VC C *2 : -1.3 at pulse width15ns which is measured at V SS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC ) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL =2mA) Symbol II(L) Min -5 Max 5 Units uA
IO(L) VOH VOL
-5 2.4 -
5 0.4
uA V V
Industrial Temperature K4E661612D,K4E641612D
DC AND OPERATING CHARACTERISTICS
Symbol Power Speed
K4E661612D -45 IC C 1 D o n t c a r e -50 -60 Normal L 90 80 70 1 1 90 80 70 100 90 80 0.5 200 130 120 110 350 350 K4E641612D 130 120 110 1 1 130 120 110 100 90 80 0.5 200 130 120 110 350 350 mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA
CMOS DRAM
(Continued) Max Units
IC C 2
D o n t c a r e
-45 IC C 3 D o n t c a r e -50 -60 -45 IC C 4 D o n t c a r e -50 -60 Normal L
IC C 5
D o n t c a r e
-45 IC C 6 D o n t c a r e -50 -60 IC C 7 IC C S L L D o n t c a r e D o n t c a r e
IC C 1* : O p e r a t i n g C u r r e n t ( R A S a n d U C A S , L C A S , A d d r e s s c y c l i n g @ t R C = m i n . ) IC C 2 : S t a n d b y C u r r e n t ( R A S = U C A S = L C A S = W = V IH ) IC C 3* : R A S - o n l y R e f r e s h C u r r e n t ( U C A S = L C A S = V IH , R A S , A d d r e s s c y c l i n g @ tR C = m i n . ) IC C 4* : E x t e n d e d D a t a O u t M o d e C u r r e n t ( R A S = V IL , U C A S o r L C A S , A d d r e s s c y c l i n g @ tH P C = m i n . ) IC C 5 : S t a n d b y C u r r e n t ( R A S = U C A S = L C A S = W = V C C - 0 . 2 V ) IC C 6* : C A S - B e f o r e - R A S R e f r e s h C u r r e n t (R A S a n d U C A S o r L C A S c y c l i n g @ t R C = m i n ) IC C 7 : B a t t e r y b a c k - u p c u r r e n t , A v e r a g e p o w e r s u p p l y c u r r e n t , B a t t e r y b a c k - u p m o d e I n p u t h i g h v o l t a g e ( V IH ) = V C C - 0 . 2 V , I n p u t l o w v o l t a g e ( V IL ) = 0 . 2 V , U C A S , L C A S = C A S - b e f o r e - R A S c y c l i n g o r 0 . 2 V W , O E = V IH , A d d r e s s = D o n t c a r e , D Q = O p e n , T R C = 3 1 . 2 5 u s IC C S : S e l f R e f r e s h C u r r e n t R A S = U C A S = L C A S = 0 . 2 V , W = O E = A 0 ~ A 1 2 ( A 1 1 ) = V C C- 0 . 2 V o r 0 . 2 V , D Q 0 ~ D Q 1 5 = V CC- 0 . 2 V , 0.2V or Open
*Note :
IC C 1 , I C C 3 , IC C 4 a n d I C C 6 a r e d e p e n d e n t o n o u t p u t l o a d i n g a n d c y c l e r a t e s . S p e c i f i e d v a l u e s a r e o b t a i n e d w i t h t h e o u t p u t o p e n . IC C i s s p e c i f i e d a s a n a v e r a g e c u r r e n t . I n I C C 1 , IC C 3 a n d I C C 6 , a d d r e s s c a n b e c h a n g e d m a x i m u m o n c e w h i l e R A S = V I L. I n I C C 4 , a d d r e s s c a n b e c h a n g e d m a x i m u m o n c e w i t h i n o n e E D O m o d e c y c l e t i m e , t HPC.
Industrial Temperature K4E661612D,K4E641612D
CAPACITANCE
( T A = 2 5 C , V C C = 3 . 3 V , f = 1 M H z ) Parameter
Input capacitance [A0 ~ A12] I n p u t c a p a c i t a n c e [R A S , U C A S , L C A S , W , O E ] Output capacitance [DQ0 - DQ15]
CMOS DRAM
Symbol
C IN1 C IN2 C DQ
Min
-
Max
5 7 7
Un i ts
pF pF pF
AC CHARACTERISTICS
( - 4 0 C T A 8 5 C , S e e n o t e 2 )
T e s t c o n d i t i o n : V CC = 3 . 3 V 0 . 3 V , V i h / V i l = 2 . 2 / 0 . 7 V , V o h / V o l = 2 . 0 / 0 . 8 V
-45 Parameter Symbol Min
Random read or write cycle time Read-modify-write cycle time Access time fromRAS Access time fromCAS Access time from column address C A S to output in Low-Z Output buffer turn-off delay from C A S O E to output in Low-Z Transition time (rise and fall) R A S precharge time R A S pulse width R A S hold time C A S hold time C A S pulse width R A S to C A S d e l a y t i m e R A S to column address delay time C A S to R A S p r e c h a r g e t i m e Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to R A S lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to R A S lead time Write command to C A S lead time Data set-up time
-50 Max Min
84 113 45 12 23 50 13 25 3 13 3 3 50 1 30 10K 50 8 38 5K 33 22 8 11 9 5 0 7 0 7 25 0 0 0 7 7 8 7 0 10K 37 25 10K 50 13 3 3 3 1 40 60 10 40 10 14 12 5 0 10 0 10 30 0 0 0 10 10 10 10 0
-60 Max Min
104 138 60 15 30
Unit Max s
ns ns ns ns ns ns 13 ns ns 50 ns ns 10K ns ns ns 10K 45 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
tRC tRWC tRAC tCAC tAA tCLZ tCEZ t OLZ tT tR P tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tW P tRWL tCWL tD S
74 101
3,4,10 3,4,5 3,10 3 6,20 3 2
3 3 3 1 25 45 8 35 7 11 9 5 0 7 0 7 23 0 0 0 7 6 8 7 0
4 10
13 13
8 8
16 9,19
Industrial Temperature K4E661612D,K4E641612D
AC CHARACTERISTICS
Parameter (Continued) -45 Min
Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time C A S to W d e l a y t i m e R A S to W d e l a y t i m e Column address to W delay time C A S set-up time ( C A S -before-R A S refresh) C A S hold time (C A S -before-R A S refresh) R A S to C A S p r e c h a r g e t i m e Access time from C A S precharge Hyper Page cycle time
CMOS DRAM
Symbol
-50 Max Min
7 64 128 64 128 0 27 64 39 5 10 5 24 28 20 47 7 200K 50 30 12 13 10 41 11 3 5 10 10 10 10 5 13 13 3 3 15 5 5 5 5 100 90 -50 13 13 13 13 52 3 5 10 10 10 10 5 3 3 15 5 5 5 5 100 110 -50 200K 25 56 10 60 35 0 32 77 47 5 10 5
-60 Max Min
10 64 128
Units Max
ns ms ms ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns ns 13 ns ns ns ns ns ns ns 13 13 ns ns ns ns ns ns ns us ns ns
Note
tD H tR E F tR E F tW C S tC W D tR W D tA W D tC S R tC H R tR P C tC P A tH P C tH P R W C tC P tR A S P tR H C P tO E A tO E D tC P W D tO E Z tO E H tW T S tW T H tW R P tW R H tD O H tR E Z tW E Z tW E D tO C H tC H O tO E P tW P E tR A S S tR P S tC H S
7
9,19
0 24 57 35 5 10 5
7 7,15 7 7 17 18
3 21 21 14
17 47 6.5 45 24
Hyper Page read-modify-write cycle time C A S precharge time (Hyper page cycle) R A S pulse width (Hyper page cycle) R A S hold time from C A S precharge O E access time O E to data delay C A S precharge to W delay time Output buffer turn off delay time from O E O E command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to R A S p r e c h a r g e t i m e ( C - B - R r e f r e s h ) W to R A S h o l d t i m e ( C - B - R r e f r e s h ) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay O E to C A S h o l d t i m e C A S hold time to OE O E precharge time W pulse width (Hyper Page Cycle) R A S pulse width (C-B-R self refresh) R A S precharge time (C-B-R self refresh) C A S hold time (C-B-R self refresh)
3
8 36 3 5 10 10 10 10 4 3 3 8 5 5 5 5 100 74 -50
6
11 11
6,20 6
22,23,24 22,23,24 22,23,24
Industrial Temperature K4E661612D,K4E641612D
TEST MODE CYCLE
-45 Parameter Symbol Min
Random read or write cycle time Read-modify-write cycle time Access time fromR A S Access time fromC A S Access time from column address R A S pulse width C A S pulse width R A S hold time C A S hold time Column Address to R A S lead time C A S to W d e l a y t i m e R A S to W d e l a y t i m e Column Address to W delay time Hyper Page cycle time Hyper Page read-modify-write cycle time R A S pulse width (Hyper page cycle) Access time fromC A S precharge O E access time O E to data delay O E command hold time
CMOS DRAM
( Note 11 )
-50 Max Min
89 121 50 17 28 50 12 18 39 28 29 62 40 22 52 50 200K 29 17 13 13 18 18 10K 10K 55 13 18 43 30 35 72 47 25 53 55 200K 33 18 20 20 55 18 30 10K 10K 65 15 20 50 35 39 84 54 30 61 65 200K 40 20
-60 Units Max Min
109 145 65 20 35 10K 10K
Note
Max
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 7 7 7 21 21 3,4,10,12 3,4,5,12 3,10,12
tR C tR W C tR A C tC A C tA A tR A S tC A S tR S H tC S H tR A L tC W D tR W D tA W D tH P C tH P R W C tR A S P tC P A tO E A tO E D tO E H
79 110
Industrial Temperature K4E661612D,K4E641612D
NOTES
1 . A n i n i t i a l p a u s e o f 2 0 0 u s i s r e q u i r e d a f t e r p o w e r - u p f o l l o w e d b y a n y 8 R A S - o n l y o r C A S - b e f o r e -R A S r e f r e s h c y c l e s b e f o r e proper device operation is achieved. 2 . I n p u t v o l t a g e l e v e l s a r e V i h / V i l . V IH ( m i n ) a n d V I L( m a x ) a r e r e f e r e n c e l e v e l s f o r m e a s u r i n g t i m i n g o f i n p u t s i g n a l s . T r a n s i t i o n t i m e s a r e m e a s u r e d b e t w e e n V IH ( m i n ) a n d V IL ( m a x ) a n d a r e a s s u m e d t o b e 2 n s f o r a l l i n p u t s . 3 . Measured with a load equivalent to 1 TTL load and 100pF. 4 . O p e r a t i o n w i t h i n t h e t R C D ( m a x ) l i m i t i n s u r e s t h a t tR A C ( m a x ) c a n b e m e t . tR C D ( m a x ) i s s p e c i f i e d a s a r e f e r e n c e p o i n t o n l y . I f t R C D i s g r e a t e r t h a n t h e s p e c i f i e d t R C D ( m a x ) l i m i t , t h e n a c c e s s t i m e i s c o n t r o l l e d e x c l u s i v e l y b y tC A C . 5 . A s s u m e s t h a t t R C D t R C D( m a x ) . 6 . T h i s p a r a m e t e r d e f i n e s t h e t i m e a t w h i c h t h e o u t p u t a c h i e v e s t h e o p e n c i r c u i t c o n d i t i o n a n d i s n o t r e f e r e n c e d t o V o h o r V o l. 7 . t W C S, tR W D , tC W D a n d t A W D a r e n o n r e s t r i c t i v e o p e r a t i n g p a r a m e t e r s . T h e y a r e i n c l u d e d i n t h e d a t a s h e e t a s e l e c t r i c c h a r a c t e r i s t i c s o n l y . I f tW C S tW C S ( m i n ) , t h e c y c l e s i s a n e a r l y w r i t e c y c l e a n d t h e d a t a o u t p u t w i l l r e m a i n h i g h i m p e d a n c e f o r t h e d u r a t i o n o f t h e c y c l e . I f tC W D t C W D ( m i n ) , t R W D t R W D ( m i n ) a n d t A W D t A W D ( m i n ) , t h e n t h e c y c l e i s a r e a d - m o d i f y - w r i t e c y c l e and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8 . E i t h e r tR C H o r t R R H m u s t b e s a t i s f i e d f o r a r e a d c y c l e . 9 . This parameters are referenced to the C A S leading edge in early write cycles and to the W falling edge in O E controlled write cycle and read-modify-write cycles. 1 0 . O p e r a t i o n w i t h i n t h e t R A D ( m a x ) l i m i t i n s u r e s t h a t tR A C ( m a x ) c a n b e m e t . tR A D ( m a x ) i s s p e c i f i e d a s a r e f e r e n c e p o i n t o n l y . I f
CMOS DRAM
t R A D i s g r e a t e r t h a n t h e s p e c i f i e d t R A D ( m a x ) l i m i t , t h e n a c c e s s t i m e i s c o n t r o l l e d b y t A A.
1 1 . These specifiecations are applied in the test mode. 1 2 . I n t e s t m o d e r e a d c y c l e , t h e v a l u e o f t R A C , tA A , tC A C i s d e l a y e d b y 2 n s t o 5 n s f o r t h e s p e c i f i e d v a l u e s . T h e s e p a r a m e t e r s should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 1 3 . t ASC, t CAH a r e r e f e r e n c e d t o t h e e a r l i e r C A S f a l l i n g e d g e . 1 4 . t CP i s s p e c i f i e d f r o m t h e l a s t C A S r i s i n g e d g e i n t h e p r e v i o u s c y c l e t o t h e f i r s t C A S f a l l i n g e d g e i n t h e n e x t c y c l e . 1 5 . tCWD is referenced to the later C A S falling edge at word read-modify-write cycle.
K4E64(6)1612D Truth Table
RAS
H L L L L L L L L
LCAS
X H L H L L H L L
UCAS
X H H L L H L L L
W
X X H H H L L L H
OE
X X L L L H H H H
DQ0 - DQ7
Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z
DQ8-DQ15
Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z
STATE
Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write -
Industrial Temperature K4E661612D,K4E641612D
1 6 . tC W L i s s p e c i f i e d f r o m W f a l l i n g e d g e t o t h e e a r l i e r C A S r i s i n g e d g e . 1 7 . tC S R i s r e f e r e n c e d t o e a r l i e r C A S f a l l i n g b e f o r e R A S t r a n s i t i o n l o w . 1 8 . tC H R i s r e f e r e n c e d t o t h e l a t e r C A S r i s i n g h i g h a f t e r R A S t r a n s i t i o n l o w .
CMOS DRAM
RAS
LCAS
UCAS
t CSR
tCHR
1 9 . tD S i s s p e c i f i e d f o r t h e e a r l i e r C A S f a l l i n g e d g e a n d tD H i s s p e c i f i e d b y t h e l a t e r C A S f a l l i n g e d g e i n e a r l y w r i t e c y c l e .
LCAS UCAS
tD S
DQ0 ~ DQ15 Din
tD H
2 0 . If R A S g o e s h i g h b e f o r e C A S high going, the open circuit condition of the output is achieved by C A S high going. 2 1 . tA S C 6 n s , A s s u m e t T = 2 . 0 n s , i f t ASC 6 n s , t h e n t H P C ( m i n ) a n d t C A S( m i n ) m u s t b e i n c r e a s e d b y t h e v a l u e o f " 6 n s - t A S C " . 2 2 . I f t R A S S 1 0 0 u s , t h e n R A S p r e c h a r g e t i m e m u s t u s e tR P S i n s t e a d o f t R P. 2 3 . F o r R A S - o n l y - R e f r e s h a n d B u r s t C A S - b e f o r e -R A S r e f r e s h m o d e , 4 0 9 6 c y c l e s ( 4 K / 8 K ) o f b u r s t r e f r e s h m u s t b e e x e c u t e d w i t h i n 64ms before and after self refresh, in order to meet refresh specification. 2 4 . For distributed C A S-before-R A S with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
Industrial Temperature K4E661612D,K4E641612D
WORD READ CYCLE
CMOS DRAM
t RC tR A S
V IH RAS V IL -
tR P
tC S H tC R P
V IH UCAS V IL -
tRCD
t RSH tC A S
tC R P
tC S H tC R P
V IH LCAS V IL -
tR C D
tR S H tC A S
tC R P
tR A D tASR
V IH A V IL -
tR A H
tASC
t RAL tC A H
COLUMN ADDRESS
ROW ADDRESS
tR C H tR C S
V IH W V IL -
tR R H
tAA tOLZ
V IH OE V IL -
tOEA tC A C tCEZ tOEZ
DATA-OUT
DQ0 ~ DQ7 VOH -
t CLZ t RAC OPEN
VOL -
tC A C
DQ8 ~ DQ15 VOH -
tCEZ tOEZ
DATA-OUT
tC L Z t RAC OPEN
VOL -
D o n t c a r e Undefined
Industrial Temperature K4E661612D,K4E641612D
LOWER BYTE READ CYCLE
N O T E : D IN = O P E N
CMOS DRAM
tRC tRAS
V IH RAS V IL -
t RP
tC R P
V IH UCAS V IL -
tR P C
t CSH tC R P
V IH LCAS V IL -
tR C D
tR S H tC A S
tR A D tASR
V IH A V IL -
t RAH
tASC
tR A L tC A H
COLUMN ADDRESS
ROW ADDRESS
tRCS
V IH W V IL -
tRCH tR R H
tC E Z tAA
V IH OE V IL -
tO E Z tOEA
tCAC
DQ0 ~ DQ7 V OH -
t CLZ t RAC OPEN
DATA-OUT
V OL -
tO L Z
DQ8 ~ DQ15 V OH -
OPEN
V OL -
D o n t c a r e
Undefined
Industrial Temperature K4E661612D,K4E641612D
UPPER BYTE READ CYCLE
N O T E : D IN = O P E N
CMOS DRAM
tR C tR A S
V IH RAS V IL -
tR P
tC S H tCRP
V IH UCAS V IL -
tRCD
tR S H tCAS
tCRP
tCRP
V IH LCAS V IL -
tR P C
tRAD t RAL tASR tR A H tASC tCAH
COLUMN ADDRESS
V IH A V IL -
ROW ADDRESS
tRCS
V IH W V IL -
tRCH tR R H
tCEZ tA A
V IH OE V IL -
tOEZ tOEA
tO L Z
DQ0 ~ DQ7 V OH -
OPEN
VOL -
t CAC
DQ8 ~ DQ15 V OH -
tC L Z tR A C OPEN
DATA-OUT
V OL -
D o n t c a r e Undefined
Industrial Temperature K4E661612D,K4E641612D
WORD WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tRC tRAS
V IH RAS V IL -
tR P
tCRP
V IH UCAS V IL -
tC S H tR C D tR S H tC A S tC R P
tCRP
V IH LCAS V IL -
tC S H tRCD tR S H tC A S tR A D tC R P
tASR
V IH A V IL -
t RAH
tASC tC A H
COLUMN ADDRESS
tR A L
ROW ADDRESS
tW C S
V IH W V IL -
tWCH tW P
V IH OE V IL -
tD S
DQ0 ~ DQ7 V IH DATA-IN V IL -
t DH
tD S
DQ8 ~ DQ15 V IH DATA-IN V IL -
t DH
D o n t c a r e Undefined
Industrial Temperature K4E661612D,K4E641612D
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tR C t RAS
V IH RAS V IL -
t RP
tCRP
V IH UCAS V IL -
tCRP tR C D
V IH LCAS V IL -
tC S H tRSH tC A S tC R P
t RAD tASR
V IH A V IL -
tRAH
tASC
tR A L tC A H
COLUMN ADDRESS
ROW ADDRESS
tWCS
V IH W V IL -
tWCH tWP
V IH OE V IL -
tD S
DQ0 ~ DQ7 V IH -
tD H
DATA-IN
V IL -
DQ8 ~ DQ15 V IH V IL -
D o n t c a r e Undefined
Industrial Temperature K4E661612D,K4E641612D
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tR C tR A S
V IH RAS V IL -
tR P
tC S H tC R P
V IH UCAS V IL -
tRCD
tRSH tCAS
tCRP
tC R P
V IH LCAS V IL -
t RAD tASR
V IH A V IL -
tR A H
tASC
t RAL tC A H
COLUMN ADDRESS
ROW ADDRESS
tWCS tW C H
V IH W V IL -
tW P
V IH OE V IL -
DQ0 ~ DQ7 V IH V IL -
t DS
DQ8 ~ DQ15 V IH DATA-IN V IL -
tD H
D o n t c a r e
Undefined
Industrial Temperature K4E661612D,K4E641612D
WORD WRITE CYCLE ( O E CONTROLLED WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tRC tRAS
V IH RAS V IL -
t RP
tC R P
V IH UCAS V IL -
t CSH tR C D tR S H tC A S tC R P
tC R P
V IH LCAS V IL -
tC S H tRCD tR S H t CAS t RAD tC R P
tASR
V IH A V IL -
t RAH
tASC
tR A L t CAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tR W L
V IH W V IL -
tW P
V IH OE V IL -
tO E D t DS
tOEH
DQ0 ~ DQ7 V IH -
tDH
DATA-IN
V IL -
t DS
DQ8 ~ DQ15 V IH -
tDH
DATA-IN
V IL -
D o n t c a r e Undefined
Industrial Temperature K4E661612D,K4E641612D
LOWER BYTE WRITE CYCLE ( O E CONTROLLED WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
t RC tR A S
V IH RAS V IL -
tR P
tCRP
V IH UCAS V IL -
tR P C
tCSH tCRP
V IH LCAS V IL -
tRCD
tR S H tCAS
tC R P
tRAD tASR
V IH A V IL -
tR A H
tASC
t RAL t CAH
COLUMN ADDRESS
ROW ADDRESS
tC W L tRWL
V IH W V IL -
tW P
V IH OE V IL -
tOED
tOEH
DQ0 ~ DQ7 V IH -
tD S
tD H
DATA-IN
V IL -
DQ8 ~ DQ15 V IH V IL -
D o n t c a r e
Undefined
Industrial Temperature K4E661612D,K4E641612D
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
N O T E : D OUT = O P E N
CMOS DRAM
tR C tR A S
V IH RAS V IL -
tR P
tC R P tR C D
V IH UCAS V IL -
tC S H tR S H tC A S tCRP
tC R P
V IH LCAS V IL -
tCRP
tR A D tASR
V IH A V IL -
t RAH
tASC
tR A L t CAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tR W L
V IH W V IL -
tW P
V IH OE V IL -
tO E D
tOEH
DQ0 ~ DQ7 V IH V IL -
DQ8 ~ DQ15 V IH -
t DS
tD H
DATA-IN
V IL -
D o n t c a r e Undefined
Industrial Temperature K4E661612D,K4E641612D
WORD READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
V IH RAS V IL -
t RP
tCRP
V IH UCAS V IL -
tR C D
tRSH tCAS
tCRP
V IH LCAS V IL -
tR C D
tRSH tCAS
t RAD tCSH tA S R tR A H tA S C t CAH
V IH A V IL -
ROW ADDR.
COLUMN ADDRESS
tA W D tC W D
V IH W V IL -
tR W L tCWL tW P
tRWD tO E A
V IH OE V IL -
tOLZ tCLZ
tC A C tO E D tOEZ
VALID DATA-OUT
tAA
DQ0 ~ DQ7 V I/OH V I/OL -
tRAC
tD S
tD H
VALID DATA-IN
tOLZ tCLZ tCAC
tA A
DQ8 ~ DQ15 V I/OH V I/OL -
tO E D tOEZ
VALID DATA-OUT
tR A C
tD S
tD H
VALID DATA-IN
D o n t c a r e
Undefined
Industrial Temperature K4E661612D,K4E641612D
LOWER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tRCD
tRSH tCAS
tRAD tCSH tASR tRAH tASC tCAH
A
VIH VIL -
ROW ADDR.
COLUMN ADDRESS
tAWD tCWD
W VIH VIL -
tRWL tCWL tW P
tRWD tOEA
OE
VIH VIL -
tOLZ tCLZ tCAC tAA
DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VOH VOL -
tRAC
tOED tOEZ
VALID DATA-OUT
tD S
tDH
VALID DATA-IN
OPEN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
UPPER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRCD
tRSH tCAS tRPC
tCRP
LCAS VIH VIL -
tRAD tCSH tASR tRAH tASC tCAH
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL -
tRWL tCWL tW P
tRWD tOEA
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL -
OPEN tOLZ tCLZ tCAC tAA tOED tOEZ
VALID DATA-OUT
DQ8 ~ DQ15 VI/OH VI/OL -
tRAC
tD S
tDH
VALID DATA-IN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE WORD READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP
tCSH tCRP
UCAS VIH VIL -
tRHCP tHPC tC P tHPC tCAS tC P tHPC tCAS tCP tCAS
tRCD
tCAS
tCRP
LCAS VIH VIL -
tREZ tRCD tRAD tRAH tASC tC P tCAS tCAS tCP tCAS tCP tCAS
tASR
A VIH VIL -
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tAA tCPA tCAC tOCH tOEA tOEA tCAC tOEP tDOH
VALID DATA-OUT
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL -
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOLZ tCLZ tCAC
DQ8 ~ DQ15 VOH VOL -
tOEP tDOH
VALID DATA-OUT
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOLZ tCLZ
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE LOWER BYTE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCRP
UCAS VIH VIL -
tRPC
tCSH tHPC tRCD tCP tCAS tCAS tCP tCAS tHPC tC P
tRHCP tHPC tCAS tREZ
LCAS
VIH VIL -
tASR
A VIH VIL -
tRAD tRAH tASC
ROW ADDR
tCAH
tASC
tCAH
tASC
tCAH tASC
COLUMN ADDR
tCAH
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tAA
OE VIH VIL -
tAA tCPA tCAC tOCH tOEA
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
tOEA tCAC
tOEP tDOH
VALID DATA-OUT
DQ0 ~ DQ7 VOH VOL -
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
DQ8 ~ DQ15 VOH VOL -
tOLZ tCLZ OPEN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE UPPER BYTE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCSH tCRP
UCAS VIH VIL -
tRHCP tHPC tC P tHPC tCAS tC P tHPC tCAS tCP tCAS tRPC
tRCD tCAS
tCRP
LCAS VIH VIL -
tRPC
tASR
A VIH VIL -
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR.
tASC
tCAH
tREZ
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRAL tRCS
W VIH VIL -
tRRH tRCH
tAA tCPA tCAC tOCH
OE VIH VIL -
tCAC tAA tCPA
tCPA tCAC tAA tCHO tOEP
tOEA tOEA
DQ0 ~ DQ7 VOH VOL -
OPEN tCAC
tOEP tDOH
VALID DATA-OUT
DQ8 ~ DQ15 VOH VOL -
tRAC
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOLZ tCLZ
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tR P tRHCP
tCRP
UCAS VIH VIL -
tHPC tRCD tCAS tHPC tRCD tCAS tRAD tCP tCAS
o
tHPC tCP tCAS
o
tRSH tCP tCAS tCRP
tCRP
LCAS VIH VIL -
tHPC tCP
tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
ROW ADDR
tCSH tASC
tCAH
tASC
tCAH
o
tASC
tCAH
COLUMN ADDRESS
COLUMN ADDRESS
o
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tW P
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
tDS
tD H
VALID DATA-IN
tD S
tDH
o
VALID DATA-IN
tDS
tDH
VALID DATA-IN
o
DQ8 ~ DQ15 VIH VIL -
tDS
tD H
VALID DATA-IN
tD S
tDH
o
VALID DATA-IN
tDS
tDH
VALID DATA-IN
o
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tRPC tCRP
UCAS VIH VIL -
tCRP
LCAS VIH VIL -
tHPC tRCD tCAS tRAD tCP tCAS
o
tHPC tC P
tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
tCSH tASC
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tW P
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
VALID DATA-IN
tD S
tD H
o
VALID DATA-IN
tD S
tD H
VALID DATA-IN
o
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tR P tRHCP
tCRP
UCAS VIH VIL -
tHPC tRCD tCAS tCP tCAS
o
tHPC tCP
tRSH tCAS tRPC
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tCSH tASC
tRAL tCAH tASC tCAH
o o
COLUMN ADDRESS
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tW P
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
o o
DQ8 ~ DQ15 VIH VIL -
tD S
tDH
VALID DATA-IN
tD S
tD H
o
VALID DATA-IN
tDS
tD H
o
VALID DATA-IN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tHPRWC tRSH
tCSH tCRP
tRCD tCAS
tCP tCAS tCP tCAS tCAS
tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRCD
tCRP
tRAD tRAH tASR
A VIH VIL ROW ADDR
tASC
COL. ADDR
tCAH tASC
COL. ADDR
tRAL tCAH
tRCS
VIH VIL -
tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDS tDH
tRCS tCWD tAWD tCPWD tOEA
tRWL tCWL tW P
W
OE
VIH VIL -
tOED tCAC tAA tOEZ tDS tDH
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
tOED tCAC tAA
DQ8 ~ DQ15 VI/OH VI/OL -
tD H tOEZ tD S
tCAC tAA tOEZ
tOED tDH tDS
tRAC tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tR P tHPRWC tRPC
tCSH tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRCD tCAS tRAD tRAH
tCP
tRSH tCAS
tCRP
tASR
A VIH VIL ROW ADDR
tASC
COL. ADDR
tCAH tASC
COL. ADDR
tCAH
tRAL
tRCS
W VIH VIL -
tCWL tWP
tRCS
tRWL tCWL tW P
tCWD tAWD tRWD tOEA tCAC tAA tOEZ tOED tD H tD S
tCWD tAWD tCPWD tOEA tOED tAA tOEZ tDH tDS
OE
VIH VIL -
tCAC
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC
tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
DQ8 ~ DQ15 VI/OH VI/OL -
OPEN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tHPRWC tRSH tCAS tRPC
tCSH tCRP
tRCD tCAS
tCP
tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRAD tRAH tASR
A VIH VIL ROW ADDR
tASC
COL. ADDR
tCAH
tASC
COL. ADDR
tCAH
tRAL
tRCS
W VIH VIL -
tCWL tWP
tRCS
tRWL tCWL tW P tCWD tAWD tCPWD
tCWD tAWD tRWD tOEA
OE
VIH VIL -
tOEA
DQ0 ~ DQ7 VI/OH VI/OL -
OPEN tOLZ tOED tCAC tAA tOEZ tD H tD S tCAC tAA tOEZ tOLZ tOED tDH tDS
DQ8 ~ DQ15 VI/OH VI/OL -
tRAC
tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HYPER PAGE READ AND WRITE MIXED CYCLE
CMOS DRAM
tRASP
RAS VIH VIL READ( tCAC) R E A D (t CPA) WRITE R E A D (tAA )
tRP
tHPC tCP
VIH UCAS VIL -
tHPC tCP tC P tCAS tHPC tCP tCAS tCAH tC P
tRHCP tHPC tCAS tHPC tCAS
tRCD
tCAS
tCAS tHPC tCP
LCAS
VIH VIL -
tRAD tASR tRAH tASC
tCAS
tCAS
tCAH
tASC
COLUMN ADDRESS
tCAH
tASC
tASC
tCAH
COL. ADDR
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
COL. ADDR
tRAL tRCS
W VIH VIL -
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE tCLZ tCPA
OE VIH VIL -
tWED
DQ0 ~ DQ7 VI/OH VI/OL -
tOEA tCAC tAA tRAC
tWEZ
tWEZ
VALID
DATA-OUT
tD H tDS
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
VALID DATA-OUT
DQ8 ~ DQ15 VI/OH VI/OL -
tOEA tCAC tAA tRAC
tWEZ
tWEZ
VALID
DATA-OUT
tD H tDS
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
VALID DATA-OUT
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Dont care DOUT = OPEN tR C
RAS VIH VIL -
CMOS DRAM
tRP
tRAS tCRP tRPC
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tASR
A VIH VIL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Dont care tRP
RAS VIH VIL -
tRC tRAS tRPC tCSR tCHR
tRP
tRPC tCP
UCAS VIH VIL -
tCP
LCAS VIH VIL -
tCSR
tCHR
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL VIH VIL -
tCEZ OPEN
OPEN tWRP tWRH
W
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tR C tRAS
tRP
tRAS
tCRP
UCAS VIH VIL -
tRCD
tRSH
tCHR
tCRP
LCAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tWRH
tRAL tAA
OE
VIH VIL -
tOEA tCEZ tREZ tWEZ tOLZ tOEZ
DATA-OUT
tCAC tCLZ
DQ0 ~ DQ7 VOH VOL -
tRAC OPEN
DQ8 ~ DQ15 VOH VOL -
OPEN
DATA-IN DATA-OUT
Dont care Undefined
* In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
Industrial Temperature K4E661612D,K4E641612D
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tR P
tR C tRAS
tR P
tRAS
tCRP
UCAS VIH VIL -
tRCD
tRSH
tCHR
tCRP
LCAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tWRH tWCS
W VIH VIL -
tWRP tWCH tW P
OE
VIH VIL -
tD S
DQ0 ~ DQ7 VIH VIL -
tD H
DATA-IN
tD S
DQ8 ~ DQ15 VIH VIL -
tD H
DATA-IN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Dont care tRP
RAS VIH VIL -
CMOS DRAM
tRASS
tRPS
tRPC tC P
UCAS VIH VIL -
tRPC tCSR tCHS
tCP
LCAS VIH VIL -
tCSR
tCHS
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL VIH VIL -
tCEZ OPEN
OPEN tWRP tWRH
W
TEST MODE IN CYCLE
NOTE : OE , A = Dont care tR C tRP
RAS VIH VIL -
tRAS
tR P
tRPC tCP
UCAS VIH VIL -
tRPC tCSR tCHR
tCP
LCAS VIH VIL -
tCSR
tCHR
W
VIL VIH -
tWTS
tWTH
DQ0 ~ DQ15 VOH VOL -
tCEZ OPEN
Dont care Undefined
Industrial Temperature K4E661612D,K4E641612D
PACKAGE DIMENSION
50 TSOP(II) 400mil
Units : Inches (millimeters)
CMOS DRAM
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25)
0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.010 (0.25) TYP 0~8
O
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45)
0.018 (0.45) 0.030 (0.75)

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